Field-programmable gate arrays (FPGAs) may be used to prototype and evaluate the performance of new processor cores that perform complex server tasks, where the FPGA may be an add-in card in a host computer. That is, prior to actually creating a new processor core in hardware, it may be advantageous to simulate the processor core with an FPGA that is connected to the host computer. Connecting the FPGA to the host computer uses common bus interfaces and protocols, such as PCI-e, HyperTransport, etc. However, a shortcoming of such interfaces and protocols (which are usually based on a serial message-passing architecture) is that there is no support for shared memory. Shared memory is an important feature of virtually all modern microprocessors, and without the ability to model or evaluate shared memory with the FPGA, all shared memory testing must be deferred until a much later date, once the proposed CPU design is actually created in hardware. This can create costly delays in testing shared memory features of the processor design, such as whether cache coherence is maintained among the various caches used by the processor. For example, FPGA caches are not snooped (e.g., to obtain a modified copy of a cache entry) by host computer caches across a PCI-e interface.